The packaging density in electronic industry continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) wafer-to-wafer stacking technology substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate, which are electrically connected using one or more wiring levels. A top layer of the wafer may be connected to a bottom layer of the wafer using interconnects or vias. In order to form a 3D wafer stack, two or more wafers are placed on top of one other and bonded, with the top and bottom wafers electrically connected using through silicon vias (TSVs). 3D stacking may also be achieved by stacking one or more individual known-good die, or chips. Chip-to-chip or chip-to-wafer stacking may be utilized to achieve 3D integration of ICs. As circuit density increases and power requirements continue to increase, heat generated during circuit operation can be a factor that adversely affects circuit reliability.